my 4 bits on FPGA

The subtle art of tricking rocks into thinking

Proper AXIS Pipelining using a Skid Buffer

A quick & basic AXI bus template

Posted on 2024-01-22

Yes, this is another blog post on the interwebz about the infamous skid buffer or AXI pipeline stages (in particular the tready path). One could think that something so essential to building AXI compliant IP is covered in detail everywhere you search. And yet, this particular IP took me longer... [Read More]
Tags:
- axi
- axis
- dsp
7400 FPGA diary 4 - Debugging the PCB

and documentation of the bitstream

Posted on 2023-12-31

Fig 1: PCB before and after assembly and debugging. [Read More]
Tags:
- diy-fpga
7400 FPGA diary 3 - Digital Twin in VHDL

simulating the FPGA bitstream before building a PCB

Posted on 2023-12-31

Fig 1: Top level diagram of a modular slice. [Read More]
Tags:
- diy-fpga
- vhdl
AXI Stream compliant DSP IP

Concepts and good practices

Posted on 2023-12-20

Somewhere at my workplace we have this complex DSP design with many FIR filters and parallel processing taking place. It is a classic case of “historical growth” where some straight forward (non AXI) bus was implemented. This can work in single rate systems with a hardcoded sample rate and a... [Read More]
Tags:
- axi
- axis
- dsp
7400 FPGA diary 2 - Transistor Level Simulation of my FPGA in VHDL

includes tricks to coerce VHDL to behave like Verilog's tranif1

Posted on 2023-12-11

Fig 1: Schematics of the simulated crosspoint switch with individual enable signals for each inout port. [Read More]
Tags:
- diy-fpga
- vhdl

Proper AXIS Pipelining using a Skid Buffer

A quick & basic AXI bus template

7400 FPGA diary 4 - Debugging the PCB

and documentation of the bitstream

7400 FPGA diary 3 - Digital Twin in VHDL

simulating the FPGA bitstream before building a PCB

AXI Stream compliant DSP IP

Concepts and good practices

7400 FPGA diary 2 - Transistor Level Simulation of my FPGA in VHDL

includes tricks to coerce VHDL to behave like Verilog's tranif1