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    my 4 bits on FPGA


    The subtle art of tricking rocks into thinking
    • 7400 FPGA diary 5 - Hello World

      program single bits in the bitstream

      Posted on 2024-03-08

      Since the completion of the most complicated modular PCB module, the CLB, I have successfully assembled the surrounding interconnect PCBs. As it turns out, you can reflow solder PCBs on the stove in your kitchen. In unrelated news, does anybody have tips on how to get rid of unwanted smells... [Read More]
      Tags:
      • diy-fpga
    • Proper AXIS Pipelining using a Skid Buffer

      A quick & basic AXI bus template

      Posted on 2024-01-22

      Yes, this is another blog post on the interwebz about the infamous skid buffer or AXI pipeline stages (in particular the tready path). One could think that something so essential to building AXI compliant IP is covered in detail everywhere you search. And yet, this particular IP took me longer... [Read More]
      Tags:
      • axi
      • axis
      • dsp
    • 7400 FPGA diary 4 - Debugging the PCB

      and documentation of the bitstream

      Posted on 2023-12-31

      Fig 1: PCB before and after assembly and debugging. [Read More]
      Tags:
      • diy-fpga
    • 7400 FPGA diary 3 - Digital Twin in VHDL

      simulating the FPGA bitstream before building a PCB

      Posted on 2023-12-31

      Fig 1: Top level diagram of a modular slice. [Read More]
      Tags:
      • diy-fpga
      • vhdl
    • AXI Stream compliant DSP IP

      Concepts and good practices

      Posted on 2023-12-20

      Somewhere at my workplace we have this complex DSP design with many FIR filters and parallel processing taking place. It is a classic case of “historical growth” where some straight forward (non AXI) bus was implemented. This can work in single rate systems with a hardcoded sample rate and a... [Read More]
      Tags:
      • axi
      • axis
      • dsp
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    Simon Burkhardt  •  2025  •  simonmartin.ch

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