Calculating the SNR from a VHDL simulation
Finding out how bad the VHDL sin function is
How to benchmark your DSP implementations using SNR
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7400 FPGA diary 7 - Final Video
Presenting my project at Cosin 2024
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7400 FPGA diary 6 - Fizz Buzz!
Building a "compiler" and adding another slice to the FPGA
I love it when a plan comes together. This blog post is about three topics: expand the FPGA by another slice, forming a 1x2 FPGA matrix programing a rudimentary assembly “compiler” so I do not have to code bits by hand runing a 4-bit counter AND a fizz-buzz detector [Read More] -
Circuit Unfolding
How to parallelize recursive DSP functions
By SimonWe are all familiar with the growing demand in computaional power in DSP applications. Radio frequency applications require processing of several gigasamples on an FPGA that can only be clocked at a maximum of several hundred of MHz. This facilitates the need to use massive parallelization of DSP algorithms -... [Read More] -
7400 FPGA diary 5 - Hello World
program single bits in the bitstream
Since the completion of the most complicated modular PCB module, the CLB, I have successfully assembled the surrounding interconnect PCBs. As it turns out, you can reflow solder PCBs on the stove in your kitchen. In unrelated news, does anybody have tips on how to get rid of unwanted smells... [Read More]