my 4 bits on FPGA

Recent live DJ sets of my favorite genre (DnB) at a genius location (Printworks) inspired something in me. And since the Printworks location is now demolished I decided to bring its visual magic into my home. [Read More]

How to benchmark your DSP implementations using SNR [Read More]

I love it when a plan comes together. This blog post is about three topics: expand the FPGA by another slice, forming a 1x2 FPGA matrix programing a rudimentary assembly “compiler” so I do not have to code bits by hand runing a 4-bit counter AND a fizz-buzz detector [Read More]

We are all familiar with the growing demand in computaional power in DSP applications. Radio frequency applications require processing of several gigasamples on an FPGA that can only be clocked at a maximum of several hundred of MHz. This facilitates the need to use massive parallelization of DSP algorithms -... [Read More]